Register Files (RF), Read Only Memories (ROMs) and Content Addressable Memories (CAMs) usage is increasing rapidly in modern microprocessor and SoC (System-on-Chip) designs due to their energy efficient local storage/access to feed various compute blocks such as Arithmetic Logic Unit (ALU), accelerators, graphics execution units, etc. Supply voltage scaling, which is an effective knob for improving energy efficiency, is governed by the memory array VMIN or the data path logic VMIN. Here, the term “VMIN” or “minimum operating voltage” generally refers to the lowest operating voltage level below which the memory will lose its data or may not function properly. Lowering the VMIN for memory (when that VMIN is the limiter) and/or reducing memory dynamic power at ISO-VMIN (when the VMIN of the logic is the limiter) is preferred for improved energy efficiency of the entire design.
Voltage-temperature stress-induced aging of p-type and n-type transistors due to NBTI (n-type bias temperature instability)/PBTI (p-type bias temperature instability) and HCl (Hot Carrier Injection) in scaled high-k/metal-gate Complementary Metal Oxide Semiconductor (CMOS) impacts maximum frequency (FMAX), VMIN, and noise margin of digital logic and Static Random Access Memory (SRAM) arrays in SoC Intellectual Property (IP) blocks over the operational lifetime. Typically, the worst-case aging impacts are included in the FMAX/VMIN settings as guardbands (or margin), and the circuits are designed for adequate noise immunity in the presence of worst-case aging degradations. Thus, significant performance and power overheads are incurred over the lifetime of the SoC.